RTL→GDSII at a glance

The OpenROAD app orchestrates a modern physical design pipeline with integrated analysis and optimization. Typical stages:

  1. Import design (LEF/DEF/Liberty/Verilog) and constraints
  2. Floorplanning, IO/tapcell insertion, PDN
  3. Global placement and clock tree
  4. Global and detailed routing
  5. Signoff checks and GDSII export

Get started quickly

Use OpenROAD Flow Scripts to run an end‑to‑end flow on example designs.

OpenROAD-flow-scripts →

Documentation

Deep‑dive documentation, recipes, and references.

User Guide →

End-to-end system view

Each stage pulls in different stakeholders and tooling. The diagram highlights how OpenROAD composes best-in-class open-source engines while mapping to the familiar commercial flow.

flowchart TB
  A["❶ Design ingest\nInputs: RTL, constraints, technology files\nPlayers: RTL & physical design leads\nOpenROAD: read_lef/def, read_liberty, link_design"] --> B
  B["❷ Floorplan & power planning\nPlayers: floorplan engineers\nOpenROAD: init_floorplan, ioPlacer, tapcell, pdngen"] --> C
  C["❸ Placement & legalization\nPlayers: placement/optimization owners\nOpenROAD: RePlAce-based global placement, OpenDP detailed placement, Resizer for CTS-aware buffering"] --> D
  D["❹ Clock tree synthesis\nPlayers: clock/PD engineers\nOpenROAD: TritonCTS + Resizer balance"] --> E
  E["❺ Routing\nPlayers: routing/DfM engineers\nOpenROAD: FastRoute global routing feeding TritonRoute detailed routing"] --> F
  F["❻ Analysis & signoff closure\nPlayers: timing, SI, DRC owners\nOpenROAD: OpenSTA, OpenRCX extraction, antenna/DRC repair"] --> G
  G["❼ Tapeout package\nPlayers: release & CAD\nOpenROAD: write_def/write_gds, lef/def clean-up"]

  classDef stage fill:#121a3a,stroke:#6e8bff,color:#ebf5ff,stroke-width:1px;
  class A,B,C,D,E,F,G stage;

  subgraph Commercial touch-points
    direction TB
    X1["Synopsys Fusion Compiler, Cadence Innovus\nread_design, floorplan GUI"]
    X2["ICC2/Innovus macro placement scripts"]
    X3["Proprietary analytic placers, ML-driven legalization"]
    X4["CTS engines (OptCTS, CCOpt)"]
    X5["GlobalRoute/RouteOpt, CDrouting"]
    X6["PrimeTime, Tempus, StarRC, Pegasus"]
    X7["StreamOut with foundry decks"]
  end

  A -. maps-to .-> X1
  B -. maps-to .-> X2
  C -. maps-to .-> X3
  D -. maps-to .-> X4
  E -. maps-to .-> X5
  F -. maps-to .-> X6
  G -. maps-to .-> X7

Stage-by-stage detail

Stage OpenROAD responsibilities Primary players Commercial counterparts
Design ingest Import tech LEF/DEF, Liberty timing, SDC constraints, and RTL netlists. Macro abstraction via `read_lef`/`read_liberty`, design assembly with `link_design`. RTL designers, PD leads, CAD for tech collateral. Fusion Compiler/ICC2 `read_design`, Innovus `set_db`. Similar file prep but locked behind vendor-specific tech plugins.
Floorplanning & PDN Hybrid automatic/manual floorplan (`init_floorplan`), IO placement with `ioPlacer`, well taps and endcaps, then mesh generation via `pdngen` with IR-drop aware grids. Floorplan engineers and packaging liaisons. Innovus floorplan editor, ICC2 plan-of-record scripts, native PDN generators with EM/IR signoff integration.
Placement & legalization Analytic global placement built on RePlAce, detailed placement (DPL) and legalization with OpenDP, buffering/sizing iterations through Resizer and Steiner guidance. Placement specialists, timing owners. Cadence GigaPlace, Synopsys EVS/ML placers with proprietary congestion predictors; often tied to license-locked machine learning optimizers.
Clock tree synthesis TritonCTS builds balanced H-trees, Resizer adjusts buffers/inverters, optional useful-skew tuning through OpenSTA. Clock/PD engineers. ICC2 CCOpt, Innovus CCOpt/Tempus integrated CTS with signoff-driven buffering.
Routing FastRoute global routing with congestion awareness feeding TritonRoute detailed routing (FlexDR engine) plus antenna/DRC repair loops. Routing owners, DFM specialists. Synopsys RouteOpt, Cadence NanoRoute with pattern-based DFM hooks and foundry-certified signoff decks.
Analysis & closure OpenSTA static timing, OpenRCX parasitic extraction, power analysis hooks, DRC antenna repair, and QoR regression metrics. Timing/SI engineers, CAD automation. PrimeTime, Tempus, RedHawk/Voltus, Pegasus/ICV for signoff; often run in parallel compute farms.
Tapeout package `write_def`/`write_gds`, final Netgen/KLayout checks, generation of LVS decks and manifest metadata. Release managers, CAD specialists. StreamOut (ICC2/Innovus), foundry-qualified DRC/LVS decks, proprietary ECO editors.